The present disclosure relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an address translation function.
Most of memory management tools in recent computers adopt a virtual memory system, and a paging scheme is known as a method of associating virtual addresses with physical addresses in the virtual memory system. In the paging scheme, each of virtual address space and physical address space is divided into continuous space units having a given size called pages, and virtual page numbers (hereinafter abbreviated as VPNs) and physical page numbers (hereinafter abbreviated as PPNs) are respectively assigned to such virtual and physical pages, to determine correspondence between such addresses.
An effective address handled in the virtual memory system is represented by the page number and the offset in the page. A system where the page size is adjustable for effective use of the memory space is generally known, and in such a system, the range of bits of an effective address indicating the page number and the range of bits thereof indicating the offset in the page are adjustable. Bits that are subjected to address translation are higher-order bits indicating the page number: lower-order bits indicating the relative address are not subjected to translation.
The correspondence between VPNs and PPNs is managed by a mechanism using both hardware and software work, called a memory management unit (MMU). A correspondence table between VPNs and PPNs (page table) is basically stored in a low-speed memory device such as an auxiliary memory device.
In general, in operation of computers, VPN to PPN translation is frequently required, and thus holds the key to improving the processing performance of the system. In particular, in high-speed oriented computers, a high-speed functional memory called a translation lookaside buffer (TLB) is incorporated in the MMU, and a copy of part of the page table is stored, or cached, in the TLB for speedup of address translation.
The circuit of the TLB generally includes a VPN memory array and a PPN memory array. During address translation, the VPN memory array is searched with higher-order bits of an effective address. Once a match VPN is found, its corresponding PPN is read from the PPN memory array.
When a high hit rate is desired, a full associative scheme is adopted for the TLB. In the full associative TLB, all entries are targets of the search. As a circuit configuration for implementing this function at high speed, the VPN memory array uses, in each memory cell, a CAM cell having a bit comparison function and a comparator having a dynamic circuit that binds bit comparison results from the CAM cell. The dynamic node of the dynamic circuit is generally called a match line. If the match line is asserted in address translation, a word line for a memory of the corresponding entry in the PPN memory array is selected, to read a desired PPN from the PPN memory array.
In a page size-adjustable TLB, a page size memory for storing the page size is provided for each entry of the address translation pair to allow adjustment of the translation range. In address translation, first, address comparison is performed, excluding some bit or bits from the target of comparison based on information stored in the page size memory for the entry in the VPN memory array. Then, the PPN of an entry of which the match line has been asserted is read from the PPN memory array. At this time, it is necessary to output the input effective address as it is for a bit or bits falling outside the translation range based on the data stored in the page size memory.
As a configuration of the PPN memory array achieving the above, a technique is known in which information is read from the page size memory for an entry of which the match line has been asserted and from the corresponding PPN memory cell simultaneously, and a selection circuit is provided on the periphery of the memory array to select either the effective address or the data stored in the PPN memory cell for a bit for which such selection is required (see Japanese Patent Publication No. H08-329687 (Patent Document 1)).
Also known is a technique in which a selection circuit for selecting either the effective address or the information stored in the PPN memory cell is provided inside the memory cell, to perform the selection before activation of the word line (see Japanese Patent Publication No. 2002-288038 (Patent Document 2)).